1. Field of the Invention
The present invention relates generally to electronic data storage devices, and more particularly, to non-volatile multi-level-cell (MLC) semiconductor memory devices and a method for maintaining read window duration in a series of programming of a multi-level-cell in a multi-bit-cell (MBC).
2. Description of Related Art
Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as Electrically Erasable Programmable Read-Only Memory (EEPROM) and flash memory are used in a variety of modern applications. A flash memory is designed with an array of memory cells that can be independently programmed and read. Sense amplifiers in a flash memory are used to determine the data value or values stored in a non-volatile memory. In a typical sensing scheme, an electrical current through the memory cell being sensed is compared to a reference current by a current sense amplifier.
A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.
As shown in FIG. 1, there is a flow diagram illustrating a conventional multi-level-cell program method 100 that programs a nitride trapping memory cell having four bits sequentially. The method 100 programs the nitride trapping memory cell sequentially, starting with a level1 programming 110, follow by a level2 programming 120, and followed by a level3 programming 130. A subsequent programming of the nitride trapping memory cell is likely to cause a complementary bit disturbance (or second bit effect), which in turn reduces the width of a read window due to a high boundary shift. This shortcoming will be further described below with respect to FIG. 2.
In FIG. 2, there is a graphical diagram 200 illustrating the sequential programming of different threshold voltage levels in the nitride trapping memory cell. The graph 200 is initially at a level0 210 after an erase. In step 1, the level1 program 220 is performed, which shows a threshold voltage distribution 225. In step 2, a level2 program 230 is performed, which shows a threshold voltage distribution 235. In step 3, a level3 program 240 is performed, which shows a threshold voltage distribution 245. Each program sequence causes a high boundary shift of lower Vt level. After the level2 program 230, there is a shift to the right in the high boundary of lower Vt level as shown in 225-2. A symbol ΔVt1 227 denotes the amount of the high boundary shift on the lower Vt level in the level1 program 220. After the level3 program 240, there is a shift to the right in the high boundary of lower Vt level in the level1 program as shown in 225-3 and there is a shift to the right in the high boundary of lower Vt level in the level2 program as shown in 235-2. A symbol ΔVt2 237 denotes the amount of the high boundary shift on the lower Vt level in level2 program 230.
With the higher level of Vt, the larger window loss occurs due to the complementary bit disturbance. As a result, the highest boundary, H region 247, dominates the amount of Vt shifts (ΔVt0, ΔVt1, and ΔVt2). The read speed is slow due to the sequence in which every level program starts from an erased Vt region.
Accordingly, it is desirable to have a multi-level-cell program method that reduces or eliminates the high boundary shift of lower Vt level in one or more nitride trapping memory cells in a memory array.